Transistor Gating Technique: Designing of Full Subtractor Circuit Implementing Sleepy Transistors in 45 nm Technology
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چکیده
منابع مشابه
Analysis and optimization of Active Power and Delay of 10T Full Adder using Power Gating Technique at 45 nm Technology
An overview of performance analysis and comparison between various parameters of a low power high speed 10T full adder has been presented here. This paper shows comparative study of advancement over active power, leakage current and delay with power supply of (0.7v) .We have achieved reduction in active power consumption of 39.20 nW and propagation delay of 10.51 ns, which makes this circuit hi...
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Micro-electronic devices are playing a very prominent role in electronic equipments which are used in daily life. For electronic equipment battery life is important. So, in order to reduce the power consumption we implement a Sleepy technique to the electronic circuits. Sleepy technique is also called as power gating technique. In the power gating structure, a circuit operates in two different ...
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ژورنال
عنوان ژورنال: International Journal of Computer Applications
سال: 2016
ISSN: 0975-8887
DOI: 10.5120/ijca2016910207